FIG. 1 is a schematic diagram of a known data transfer system 100. Data transfer system 100 includes a data link 102 which receives data read transfers and data write transfers from a host (not shown) and transfers the data read transfers and data write transfers to a disk drive system (not shown) through a multi-port access architecture 104 for the purpose of reading data from and writing data to the disk drive system. Data transfer system 100 includes a FIFO buffer 106 which receives the data read transfers and data write transfers from the data link 102, and an output register 108, which is controlled by output register controller 110.
In operation, in the example shown in FIG. 1, a data write transfers 112, including a header “WRITE” and the data to be written, DATA1-DATA8, are input to the FIFO buffer 106 through the data link 102. Several data read transfers, “READ” 114, are then input to the FIFO buffer 106. Each data transfer is transferred to the output register 108 in the order that it was received by the FIFO buffer 106. The output register 108 processes each data transfer and transfers each data transfers to the proper port, as indicated in the header associated with the data transfer. The output register 108 processes the data read and write transfers one at a time as it transfers each through to the multi-port access architecture 104.
Although the combination of the single FIFO buffer 106 and the output register 108 are suitable for use with low-traffic systems, it becomes limited as the data traffic increases. Since the single FIFO buffer 106 and the output register 108 can process only one data transfer at a time, if a particular transfer cannot be completed because the client, or disk drive, to which the data transfer is directed, or the port through which the transfer is to occur, is not able to process the request, or takes a longer time than expected to process the request, the data transfer system stalls. No further transfers can be processed because the output register 108 holds the current data transfer until it can be processed, thus preventing subsequent transfers from being processed. The FIFO buffer 106 is still able to receive incoming data read and write requests from the data link 102, but the data requests in the FIFO buffer will remain backlogged until the data transfer in the output register 108 is processed. In the example shown in FIG. 1, if the data write transfer 112 is not able to be processed by the disk drive system coupled to multi-port access architecture 104, none of the data read requests 114 that follow the data write request 112 in the FIFO buffer 106 will be able to be processed until the data write request is processed. This can severely impede the operation of the data transfer system.